Capacitors are one type of component commonly used in the fabrication of integrated circuits, for example in DRAM and other memory circuitry. A capacitor is comprised of two conductive electrodes separated by a non-conducting dielectric region. As integrated circuitry density has increased, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing capacitor area. The increase in density has typically resulted in greater reduction in the horizontal dimension of capacitors as compared to the vertical dimension. In many instances, the vertical dimension of capacitors has increased.
One manner of fabricating capacitors is to initially form an insulative material within which a capacitor storage node electrode is formed. For example, an array of capacitor electrode openings for individual capacitors may be fabricated in such insulative capacitor electrode-forming material, with an example material being silicon dioxide doped with one or both of phosphorus and boron. The capacitor electrode openings may be formed by etching. It can be difficult to etch such openings within the insulative material, particularly where the openings are deep.
Further and regardless, it is often desirable to etch away most if not all of the capacitor electrode-forming material after individual capacitor electrodes have been formed within the openings. Such enables outer sidewall surfaces of the electrodes to provide increased area and thereby increased capacitance for the capacitors being formed. However, capacitor electrodes formed in deep openings are often correspondingly much taller than they are wide. This can lead to toppling of the capacitor electrodes, either during etching to expose the outer sidewalls surfaces, during transport of the substrate, and during deposition of the capacitor dielectric layer and/or outer capacitor electrode layer. U.S. Pat. No. 6,667,502 teaches the provision of a brace or retaining structure intended to alleviate such toppling. Other aspects associated in the formation of a plurality of capacitors, some of which include bracing structures, are also disclosed and are:                U.S. Pat. No. 7,067,385;        U.S. Pat. No. 7,125,781;        U.S. Pat. No. 7,199,005;        U.S. Pat. No. 7,202,127;        U.S. Pat. No. 7,387,939;        U.S. Pat. No. 7,439,152;        U.S. Pat. No. 7,517,753;        U.S. Pat. No. 7,544,563;        U.S. Pat. No. 7,557,013;        U.S. Pat. No. 7,557,015;        U.S. Patent Application No. 2008/0090416;        U.S. Patent Application No. 2008/0206950;        U.S. Pat. No. 7,320,911;        U.S. Pat. No. 7,682,924;        U.S. Patent Application No. 2010/0009512;        
Fabrication of capacitors in memory circuitry may include forming an array of capacitors within a capacitor array area. Control or other circuitry area is often displaced from the capacitor array area, and the substrate may include an intervening area between the capacitor array area and the control or other circuitry area. In some instances, a trench is formed in the intervening area between the capacitor array area and the other circuitry area. Such trench may be formed commensurate with the fabrication of the openings within the capacitor array area within which the isolated capacitor electrodes will be received.